1. Field of the Invention
The present invention relates in general to metal-oxide semiconductor field-effect transistors (MOSFETs). In particular, the present invention relates to metal-oxide semiconductor field-effect transistors having an improved source/drain structural configuration and a method of fabricating the same.
2. Technical Background
Metal-oxide semiconductor field-effect transistors, here, after referred to as MOSFETs, are a major constituent of integrated circuits (IC) because they can be miniaturized in dimension to a greater extent than can many other devices. A natural consequence of the trend toward improved fabrication resolutions for integrated circuit devices is that such devices continue to shrink in size, down to the sub-micron level at present. The dimensions of MOSFETs found on IC substrates are shrinking and not only are they shrinking in planar directions, but the dimensions in the direction perpendicular to the surface of the IC device substrate are also being reduced simultaneously. If the depth of the MOSFET components is not reduced along with the reduction of their surface area dimensions, problems, such as electron punchthrough, may arise.
It is therefore desirable for integrated circuit MOSFETs to have not only a reduced planar dimension, but also a relatively shallow junction in the source/drain regions. Although a shallow junction reduces the disadvantage of short channel effect, the sheet resistance of the source/drain regions is increased as a result of the reduced cross-sectional area of the junctions. Unfortunately, if the doping concentration in the junctions is increased to reduce the resistance, then the hot electron effect resulting from the increased electric field generated by the heavily doped source/drain regions inevitably reduces the reliability of the MOSFETs.
In order to keep the resistance in the source/drain regions of the MOSFETs reasonably low while the dimensions of the IC device are reduced without increasing the electric field intensity in the source/drain regions, a transistor having a lightly-doped source/drain configuration has been proposed. FIG. 1A shows a cross-sectional view of the structural configuration of such a prior art transistor having a lightly-doped source/drain junction. In fabricating this prior art transistor, a field oxide layer 11, a gate oxide layer 12, and a polysilicon gate layer 13 are formed over a P-type substrate 10. An ion implantation process is employed to implant N-type impurities, such as phosphorus, into the P-type substrate 10 by using the polysilicon gate layer 13 as a mask to form lightly-doped N.sup.- -conductivity type source/drain regions 14. Conventional deposition and etching procedures are then employed to form oxide spacers 15 on opposing side walls of the gate oxide layer 12 and the polysilicon gate layer 13. Finally, impurities, such as arsenic (As) or antinomy (Sb), are implanted into the P-conductivity type substrate 10 to form N.sup.+ -conductivity type source/drain regions 16 for the
The structural configuration of this transistor prevents the hot electron effect because the source/drain regions 14 are tightly doped, which reduces the build-up of an electric field of excessive intensity near the drain, and because the source/drain regions 16 have a high doping concentration, which maintains a reasonable resistance value by itself. With the above transistor structural configuration, it should be noted, however, that the junction interface of the N.sup.+ -conductivity type source/drain region 16 and the P-conductivity type substrate 10 results in the generation of parasitic capacitance. The larger the junction interface area, the larger the parasitic capacitance, which reduces the speed of operation of this transistor device.
Moreover, an improvement in the conductivity of the source/drain regions 16 can be realized by employing the well-known technique of self-aligned silicide (salicide) to form a conducting layer on an appropriate place on the surface of the device.
The process for forming such salicide involves depositing metals such as Ti, Co, Ni, and Pt on the device surface. For example, when Ti metal is utilized, a Rapid Thermal Process (RTP) at a temperature of approximately 650.degree. C. is performed for 20 to 60 seconds, and the portions with non-reacted metal are selectively removed by dipping the device surface in appropriate chemical solutions. In the case of Ti, portions containing silicon react with the metal, while portions containing silicon oxide do not. Then a solution of NH.sub.4 OH/H.sub.2 O.sub.2 /H.sub.2 O is employed to etch away the unreacted Ti film and Ti.sub.5 Si.sub.3, TiN.sub.x O.sub.y etc. A second thermal process at a temperature of approximately 850.degree.0 C. is performed for 20 to 60 seconds to allow the metal salicide 17 to achieve the crystalline phase of greatest stability and lowest resistivity, with a typical structural configuration as shown in FIG. 1B. Although such salicide fabricating process improves the conductivity of the source/drain regions, it also deepens the junction of the source/drain regions 16, which is undesirable because of the need for shallow junctions in the source/drain regions 16.